eSTREAM: the ECRYPT Stream Cipher Project
Welcome to the home page of eSTREAM, the ECRYPT Stream Cipher Project. The eSTREAM project was a multi-year effort, running from 2004 to 2008, to promote the design of efficient and compact stream ciphers suitable for widespread adoption. As a result of the project, a portfolio of new stream ciphers was announced in April 2008. The eSTREAM portfolio was revised in September 2008, and currently contains seven stream ciphers. This website is dedicated to ciphers in this final portfolio. For information on the eSTREAM project and selection process, including a timetable of the project and further technical background, please visit the original eSTREAM Project website.
The eSTREAM Portfolio
The short report from April 2008 discussing the initial portfolio (with eight stream ciphers) and the end of the eSTREAM project can be found here. The eSTREAM portfolio was revised in September 2008, following the announcement of cryptanalytic results against one of the original algorithms (see here). The portfolio is periodically revisited, as the algorithms mature: the first review of the eSTREAM portfolio was published in October 2009, and is available here; the second review from January 2012 can be found here.
The eSTREAM portfolio ciphers fall into two profiles. Profile 1 contains stream ciphers more suitable for software applications with high throughput requirements. Profile 2 stream ciphers are particularly suitable for hardware applications with restricted resources such as limited storage, gate count, or power consumption.
The eSTREAM portfolio contains the following ciphers:
The eSTREAM Book
New Stream Cipher Designs - The eSTREAM Finalists, a volume published by Springer in 2008, provides full specifications of all 16 ciphers that reached the final phase of the eSTREAM project, implementation surveys covering both the software- and the hardware-oriented finalists.
Implementation and Performance
Hardware performance of all profile-2 eSTREAM candidates (phase 3) was described in Good and Benaissa's paper at SASC 2008 (article). Prototype quantities of an ASIC containing all phase-3 hardware candidates was designed and fabricated on 0.18 μm CMOS, as part of the eSCARGOT project.
- eSTREAM Project website
- eSTREAM book
- eSTREAM Portfolio Documents:
- Software Implementation and Performance:
- Hardware Implementation and Performance: